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Silicon Nanoelectronics: Demonstration of a new approach for nanoscale silicon electronics

In a major step towards enabling high performance silicon electronics smaller than existing scaling limits, CNS researchers have demonstrated the first circuits and transistors in a new nanoscale-compatible device geometry. In this approach two aligned gate electrodes are produced on opposite sides of a planar silicon channel only a few t0’s of nanometer (nm) thick. This is achieved via a technique that exfoliates a single-crystal silicon layer from one wafer and transfers it to another. The novel structure is scalable to dimensions at the 10’s of nm scale. This placement of control gates on both sides of the silicon channel also allows the operational properties of the device to be controlled by altering the back gate voltage. For example the same device structure can be operated with a back gate voltage that results in a transistor that requires very low stand-by power, or at a different back gate voltage that results in very high speed transistor operation.

[Lead CNS Investigator: S. Tiwari]

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