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A new approach for nanoscale si-electronics

One of the key challenges for nanoelectronics is the development of a versatile nanoscale transistor structure that exhibits well-controlled and dynamically tunable electrical characteristics when shrunk down to very small dimensions of the order of 10 nanometers (10 billionths of a meter). It is particularly desirable for this new transistor to be able to function both as a high performance logic switch and as a low power memory element. Then billions of such elements could be connected together without requiring excessive power dissipation, a major problem in conventional microelectronics. The result of such a versatile transistor element would be nanoelectronics performance that is superior to what is possible with today's approaches to silicon electronics. CNS researchers have now demonstrated the first such nanoscale silicon-based transistor and memory device that provides this critical, tunable attribute. The fabrication of this structure is achieved via a technique that exfoliates a single crystal Si layer only several hundred atoms thick from one Si wafer and transfers it to another. This exfoliation process facilitates the fabrication of electrical control contacts or gates on both sides of the Si channel, which results in excellent nanoscale transistor properties.

A scanning electron microscope image of the cross-section of the new nanoscale silicon transistor.

[Lead CNS Investigator: S. Tiwari]

For additional information see:
  • U. Avci and S. Tiwari, "Nano-Scale Thin Single-Crystal Silicon and its Application to Electronics," Appl. Phys. Lett., 84, 13, 2406-2408 (2004)
  • U. Avci and S. Tiwari, "Back-Gated MOSFETs with Controlled Silicon Thickness MOSFETs for Adaptive Threshold Voltage Control," Electronic Letters, 40, No. 1 (2004)
  • U. Avci, A. Kumar and S. Tiwari, "Theoretical and Experimental Analysis of Back-Gated SOI MOSFETs and Back-Floating NVRAMs," J. of Semiconductor Technology and Science, 4, No. 1, 18(2004)
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