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Three-dimensional integration of silicon nanoelectronics

Individual electronic components such as computer logic and memory chips essentially have a planar geometry and information transport between components has to take place over relatively large distances resulting in sub-optimal performance. Although industry has been working on the three-dimensional integration of silicon based devices for many years , the technology developed by CNS researchers for fabricating nanoscale Si double-gated transistors with buried gates from ultra-thin layers of single-crystal has the potential for quite broad usage, as it allows the transfer of wafer-scale layers of active devices onto foreign substrates. A team of CNS and MIT Lincoln Laboratories researchers have implemented a simple 8 bit microprocessor consisting of 3 silicon tiers using approximately 33000 standard cells, with the input and output instruction on the first layer, the instruction decoding and logic unit on the second layer and the memory on the third layer. This the first implementation of a three-dimensional microprocessor ever reported

Scanning Electron Microscope image of a cross section of a stack of 4 device layers consisting of double gated silicon transistor technology.

[Lead CNS Investigator: Tiwari group - Nanoelectronics Thrust, Center for Nanoscale Systems, Cornell University]

For additional information see:

  • S. Tiwari, C. C. Liu and S. K. Kim, “Device, Circuit and System Dimensions of 3-D Integration,” Invited Paper, Tech. Dig. of IEEE Device Research Conference, June, 33-34(2006)
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